Point contact array, not circuit, and electronic circuit comprising the same

ABSTRACT

A point contact array, including plural point contacts electrically and reversibly controlling conductance between electrodes and being applicable to an arithmetic circuit, a logic circuit, a memory device, a NOT circuit, and an electronic circuit including the same. The circuit includes plural point contacts each including a first electrode made of a compound conductive material having ionic conductivity and electronic conductivity and a second electrode made of a conductive substance. The conductance of each point contact is controlled to realize the circuit. Ag 2 S, Ag 2 Se, Cu 2 S, or Cu 2 Se is preferably used as the compound conductive material. When a semiconductor or insulator material is interposed between the electrodes, a crystal or an amorphous material of GeS x , GeSe x , GeTe x , or WO x  (0&lt;x&lt;100) is preferably used as the semiconductor or insulator material. The NOT circuit is realized using a device including an atomic switch serving as a two-terminal device, the device including a first electrode made of a compound conductive material having ionic conductivity and electronic conductivity and a second electrode made of a conductive substance, and capable of controlling conductance between the electrodes.

TECHNICAL FIELD

The present invention relates to a point contact array comprising aplurality of devices in each of which a point contact is formed ordisconnected between electrodes facing each other to controlconductance, a NOT circuit, and an electronic circuit using the same,and more particularly to a NOT circuit comprising an electronic device(an atomic switch which will be described below) in which a pointcontact is formed or disconnected between electrodes facing each otherto control conductance, and an electronic circuit using the same.

BACKGROUND ART

As related arts [1], methods for forming a point contact to controlconductance are disclosed by, for example, J. K. Gimzewski and R.Moller: Phys. Rev. B36, p1284, 1987, J. L. Costa-Kramer, N. Garcia, P.Garcia-Mochales, P. A. Serena, M. I. Marques, and A. Corrcia: Phys. Rev.B55, p5416, 1997, and H. Ohnishi, Y. Kondo, and K. Takayanagi: Nature,Vol. 395, p780, 1998.

Each of these methods requires a piezo device in order to form andcontrol each point contact. In other words, a metallic probe equippedwith the piezo device is positioned with respect to an oppositeelectrode with high precision by driving the piezo device, thus forminga point contact between the probe and the opposite electrode. The statethereof is controlled.

In addition to these arts, as a related art [2], a method forcontrolling conductance of each point contact, the method using organicmolecules is disclosed by C. P. Collier et al.: Science, Vol. 285, p391,1999.

According to this method, the conductivity of rotaxane molecules of onemolecule thickness sandwiched by electrodes facing each other is changedby applying high voltage between the electrodes. In other words, therotaxane molecules, sandwiched between the electrodes, initially exhibitthe conductivity. When a predetermined or higher voltage of a certainpolarity is applied, the molecules are oxidized to reduce theconductivity, so that the electrodes are isolated from each other.

[3] Hitherto, it is known that an AND circuit and an OR circuit can beformed using a diode serving as a two-terminal device.

On the other hand, it is also well-known that a NOT circuit cannot beformed using only the diode. In other words, the NOT circuit cannot beformed using only the conventional two-terminal devices. Accordingly,the formation of the NOT circuit requires a transistor serving as athree-terminal device.

All of logic circuits can be constructed using the combination of theAND circuit, the OR circuit, and the NOT circuit. In other words, athree-terminal circuit is indispensable to the formation of an arbitrarylogic circuit. This fact is described in detail in, for example, “NYUMONELECTRONICS KOHZA (Library of Introduction to Electronics) DigitalCircuit”, Vol. 2, pages 1 to 7, published by Nikkan Kogyo Shinbun Co.,Ltd. (I).

Nowadays as the integration of silicon devices is approaching its limit,new nanometer-sized devices such as molecular devices are beingdeveloped. For example, the result of the experiment of a transistorusing a carbon nanotube is described in Nature, Vol. 393, pages 49 to50, 1998 (II).

DISCLOSURE OF INVENTION

According to the method of the foregoing related arts [1], however, onepoint contact needs at least one piezo device and a complicated controlcircuit for driving the device. It is very difficult to integrate thesecomponents.

According to the method of the foregoing related art [2], sincetemporarily oxide molecules are reduced and the conductivity cannot berestored, the application is remarkably restricted. Further, for [3],the foregoing three-terminal circuit becomes a factor to inhibitminiaturization.

For example, according to the method of the foregoing document (II), astructure such as a gate other than the carbon nanotube is formed byapplying an existing process for manufacturing a semiconductor device.Accordingly, the size of the entire transistor is not so different fromthat of the conventional transistor. In other words, actually, thedevelopment of nanometer-sized devices still remains in the stage ofdemonstrations of the fundamental principle.

In consideration of the above situations, a first object of the presentinvention is to provide a point contact array including a plurality ofpoint contacts each of which electrically and reversibly controlsconductance between electrodes and each of which is applicable to anarithmetic circuit, a logic circuit, and a memory device.

A second object of the present invention is to provide a NOT circuitincluding a nanometer-sized electronic device and an electronic circuitusing the same.

To accomplish the above objects, according to the present invention,

[1] there is provided a point contact array including a plurality ofelectronic devices, each of which includes a first electrode made of acompound conductive material having ionic conductivity and electronicconductivity and a second electrode made of a conductive substance andeach of which can control conductance between the electrodes.

[2] In the point contact array described in [1], preferably, thecompound conductive material having mobile ions (M ion: M denotes ametallic atom) is formed on a source of the mobile ions (M).

[3] In the point contact array described in [1] or [2], preferably, thecompound conductive material is Ag₂S, Ag₂Se, Cu₂S, or Cu₂Se.

[4] In the point contact array described in [1], [2], or [3],preferably, the mobile ions, contained in the compound conductivematerial, form a bridge between the first and second electrodes tochange the conductance between the electrodes.

[5] In the point contact array described in [1], [2], or [3],preferably, a semiconductor or insulator material, which can dissolveions and which exhibits electronic conductivity and ionic conductivitydue to the dissolution of ions, is arranged between the first and secondelectrodes, and mobile ions contained in the compound conductivematerial enter the semiconductor or insulator material to change theconductance of the semiconductor or insulator.

[6] In the point contact array described in [5], preferably, thesemiconductor or insulator material is a crystal or an amorphousmaterial of GeS_(x), GeSe_(x), GeTe_(x), or WO_(x) (0<x<100).

[7] In the point contact array described in [1], [2], [3], [4], [5], or[6], preferably, a metallic wire, of which at least one part is coveredwith the compound conductive material, functions as the first electrode,a metallic wire functions as the second electrode, a plurality ofmetallic wires functioning as at least one of the electrodes exist, anda point contact is arranged at each intersection of the metallic wires.

[8] In the point contact array described in [1], [2], [3], [4], [5],[6], or [7], preferably, the conductance of each point contact isquantized.

[9] The point contact array described in [8] may function as a multiplerecording memory device in which the quantized conductance of each pointcontact is used as a recording state.

[10] In the point contact array described in [8], preferably, thequantized conductance of each point contact is used as an input signal,and the potentials of the respective electrodes are controlled toperform addition or subtraction of the input signals.

[11] The point contact array described in [1], [2], [3], [4], [5], [6],or [7] may function as a logic circuit in which a potential at one endof each point contact is used as an input signal.

[12] There is provided a NOT circuit including only two-terminaldevices.

[13] There is provided a NOT circuit including an atomic switch servingas a two-terminal device.

[14] In the NOT circuit described in [13], preferably, the atomic switchincludes a device, which includes a first electrode made of a compoundconductive material having ionic conductivity and electronicconductivity and a second electrode made of a conductive substance andwhich can control conductance between the first and second electrodes.

[15] In the NOT circuit described in [14], preferably, the compoundconductive material is Ag₂S, Ag₂Se, Cu₂S, or Cu₂Se.

[16] The NOT circuit described in [14] or [15] may include a resistorand a capacitor, each of which serves as a two-terminal device, inaddition to the atomic switch.

[17] The NOT circuit described in [16] may include a diode in additionto the resistor and the capacitor.

[18] In the NOT circuit described in [16], preferably, a voltage to beapplied to the atomic switch is controlled through the capacitor tocontrol the conductance of the atomic switch.

[19] There is provided an electronic circuit including a combination ofthe NOT circuit described in any one of [13] to [18], and an AND circuitand an OR circuit, each of which includes the atomic switch.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic perspective view showing a point contact array, inwhich a plurality of point contacts are arranged, according to thepresent invention.

FIG. 2 is a schematic view showing a point contact array constituting amultiple storage memory according to the present invention.

FIG. 3 shows the result of reading of the multiple storage memoryaccording to a first embodiment of the present invention.

FIG. 4 shows the result of an arithmetic operation by an adding circuitcomprising a point contact array according to a second embodiment of thepresent invention.

FIG. 5 shows the result of an arithmetic operation by a subtractingcircuit comprising a point contact array according to a third embodimentof the present invention.

FIG. 6 is a schematic diagram of an OR gate comprising a point contactarray according to a fourth embodiment of the present invention.

FIG. 7 shows the results of the operation of an OR gate comprising apoint contact array according to the fourth embodiment of the presentinvention.

FIG. 8 is an equivalent circuit diagram of a point contact array logiccircuit according to the fourth embodiment of the present invention.

FIG. 9 is a schematic diagram of an AND gate comprising a point contactarray according to a fifth embodiment of the present invention.

FIG. 10 shows the results of the operation of the AND gate comprisingthe point contact array according to the fifth embodiment of the presentinvention.

FIG. 11 is a view showing a method for forming a point contact arrayaccording to a sixth embodiment of the present invention.

FIG. 12 is a schematic view of a point contact array according to aseventh embodiment of the present invention, the point contact arraycontrolling the conductivities of semiconductors.

FIG. 13 is a schematic view of a point contact array according to aneighth embodiment of the present invention, the point contact arrayhaving electrodes partially covered with a compound conductor.

FIG. 14 is a schematic diagram of a NOT circuit according to a ninthembodiment of the present invention.

FIG. 15 includes graphs showing a principle of the operation of the NOTcircuit according to the ninth embodiment of the present invention.

FIG. 16 is a schematic diagram of a NOT circuit according to a tenthembodiment of the present invention.

FIG. 17 includes graphs showing a principle of the operation of the NOTcircuit according to the tenth embodiment of the present invention.

FIG. 18 is a schematic diagram of a NOT circuit according to an eleventhembodiment of the present invention.

FIG. 19 includes graphs showing a principle of the operation of the NOTcircuit according to the eleventh embodiment of the present invention.

FIG. 20 is a schematic diagram of a NOT circuit according to a twelfthembodiment of the present invention.

FIG. 21 is a schematic diagram of a one-digit binary adder according toa thirteenth embodiment of the present invention.

FIG. 22 is a diagram showing logical symbols of the one-digit binaryadder according to the thirteenth embodiment of the present invention.

FIG. 23 is a diagram showing a truth table of the one-digit binary adderaccording to the thirteenth embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described in detailhereinbelow with reference to the drawings.

FIG. 1 is a schematic perspective view showing a point contact array, inwhich a plurality of point contacts are arranged, according to thepresent invention.

As shown in FIG. 1, point contacts (bridges) 6 and 7 each comprisingmobile ions (atoms) 5 are formed at the intersections of a metallic wire(first electrode) 2 and metallic wires (second electrodes) 3 and 4, themetallic wire 2 being covered with an electronic/ionic mixed conductor1. These components are arranged on an insulating substrate 8 and arethen fixed thereto using an insulating material (not shown).

When a semiconductor or insulator material is interposed between thefirst and second electrodes, mobile ions are dissolved into thesemiconductor or insulator to change the conductance of thesemiconductor.

Consequently, the conductance between the electrodes is changed. Theamount of change depends on the amount of the mobile ions dissolved inthe semiconductor or insulator material.

For the sake of simplification, FIG. 1 shows the point contact arraycomprising the one metallic wire (first electrode) 2, covered with theelectronic/ionic mixed conductor 1, and the two metallic wires (secondelectrodes) 3 and 4. The number of point contacts is obtained bymultiplying the number of metallic wires each constituting theelectrode. In this case, 2×1, namely, two point contacts are formed.When the number of metallic wires constituting the first and secondelectrodes is increased, a point contact array having n×n point contactscan be formed.

According to the present invention, a voltage is applied between thefirst electrode 2 and the second electrodes 3 and 4, resulting in theformation or disappearance of the bridges 6 and 7 comprising ion atoms.Thus, the conductance of each point contact formed between theelectrodes is controlled. Specifically, when a proper negative voltageis applied to the second electrodes 3 and 4 with respect to the firstelectrode 2, mobile ions (atoms) in the electronic/ionic mixedconductive material are precipitated due to effects of voltage andcurrent, resulting in the formation of the bridges 6 and 7 between theelectrodes. Consequently, each conductance between the electrodes isincreased. On the other hand, when a proper positive voltage is appliedto the second electrodes 3 and 4, the mobile ions (atoms) return to theelectronic/ionic mixed conductive material, resulting in thedisappearance of the bridges 6 and 7. In other words, the conductance isreduced.

As mentioned above, a voltage applied to each metallic wire isindependently controlled, so that a voltage applied to the point contactformed at each of the intersections of the first electrode 2 and thesecond electrodes 3 and 4 can be independently controlled. In otherwords, the conductance of the point contact at each intersection can beindependently controlled.

In this manner, an electronic device such as a memory device or anarithmetic device comprising a point contact array and an electriccircuit comprising the electronic devices can be formed.

Embodiments using a first electrode comprising an electronic/ionic mixedconductive material of Ag₂S and an Ag which is a source of mobile ionsof Ag and second electrodes comprising Pt will now be describedhereinbelow. It is needless to say that the similar results can beobtained using other materials.

When there are about ten atoms of Ag, each bridge can be sufficientlyformed. On the basis of the measurement result, on condition that avoltage is 100 mV and initial interelectrode resistance is 100 kΩ, thetime required to derive ten Ag atoms from Ag₂S serving as theelectronic/ionic mixed conductor, namely, the time required to form abridge is estimated to be tens of nanoseconds at most. An electric powerrequired to form the bridge is on the order of nanowatts, namely, thepower is small. Accordingly, the application of the present inventionrealizes the construction of a high-speed device with low powerconsumption.

A first embodiment of the present invention will now be described.

FIG. 2 shows a schematic view of a point contact array according to thepresent invention, the point contact array being applied to a multiplememory device.

For the sake of simplification, a sample comprising two point contactsis used in a manner similar to FIG. 1. In this case, Ag₂S is used as anelectronic/ionic mixed conductive material 11 functioning as a firstelectrode and an Ag wire is used as a metallic wire 10. Pt wires areused as metallic wires 13 and 14 each functioning as a second electrode.The first electrode is grounded and voltages V1 and V2 are independentlyapplied to the second electrodes 13 and 14, respectively. When negativevoltages are used as V1 and V2, Ag atoms 12 contained in theelectronic/ionic mixed conductive material 11 are precipitated to formbridges 15 and 16. When positive voltages are used as V1 and V2, the Agatoms 12 in the bridges 15 and 16 return to the electronic/ionic mixedconductive material 11, resulting in the disappearance of the bridges 15and 16. Japanese Patent Application No. 2000-265344, by the inventors ofthe present application, proposes the detailed mechanism.

According to the present invention, the use of a plurality of pointcontacts realizes a new function, which will be described hereinbelow.

According to the present embodiment, pulse voltages are applied tocontrol the conductance of each point contact. In other words, in orderto increase the conductance, a voltage of 50 mV is applied for 5 ms. Inorder to reduce the conductance, a voltage of −50 mV is applied for 5ms. Thus, transition in the quantized conductance of each point contactis realized. In other words, the transition corresponds to the writingoperation of the memory.

In order to read a recording state, V1 and V2 are set to 10 mV so thatthe recorded conductance is not changed by the reading operation. Inthis situation, current I₁ and I₂ flowing through the metallic wires 13and 14, each functioning as the second electrode of the point contact,are measured. FIG. 3 shows the result.

Referring to FIG. 3, I₁ is shown by a thin solid line and I₂ is shown bya thick solid line. The point contact 15 or 16 is subjected to thewriting operation every second. The recording state is read out aftereach writing operation. The ordinate axis on the left denotes a currentactually measured. The ordinate axis on the right denotes quantizedconductance corresponding thereto. The conductance is obtained bydividing the measured current by the applied voltage (10 mV).

It is understood from the graph that the conductance of each pointcontact is quantized. In other words, when it is assumed that N₁ denotesthe quantum number of the quantized conductance of a first point contactserving as the bridge 15 and N₂ denotes the quantum number of thequantized conductance of a second point contact serving as the bridge16, N₁=0 to 3 and N₂=0 to 3, namely, 16 recording states are realized intotal.

According to the present embodiment, four quantized states of N=0 to 3are used. If a state having a larger quantum number is used, therecording density can be increased. It is needless to say that therecording density can also be increased by increasing the number ofpoint contacts.

A second embodiment of the present invention will now be described.

First, an example in which an adding circuit is realized with theconfiguration shown in the first embodiment will be described.

According to the present invention, inputs denote the quantum numbers N₁and N₂ of the quantized conductance of the point contacts serving as thebridges 15 and 16. The input operation is performed by controlling thevoltages V1 and V2 to set each of N₁ and N₂ to a desired value. V1 andV2 are set to a reading voltage, for example, 10 mV and a currentI_(out) flowing from the first electrode 10 to a ground potential ismeasured, thus obtaining the result of an arithmetic operation.

FIG. 4 shows the result of the arithmetic operation according to thesecond embodiment of the present invention. Below a graph, the inputtedN₁ and N₂ and measured N_(out) are shown so as to correspond to theabscissa axis of the graph. It is found that the obtained currentI_(out) has quantized conductance corresponding to (N₁+N₂). In otherwords, the addition is correctly performed. According to the presentembodiment, 16 addition results corresponding to N₁=0 to 3 and N₂=0 to 3are shown in the same way as the first embodiment. Larger quantumnumbers can also be used. For the number of point contacts used, namely,the number of inputs, three or more inputs can also be used.

A third embodiment of the present invention will now be described.

The configuration shown in the first embodiment can also be applied to asubtracting circuit. Inputs are controlled by the same method describedin the second embodiment. Upon subtraction, voltages, which have thesame absolute value and whose polarities are opposite to each other, canbe used as V1 and V2. For example, when V1 is set to 10 mV and V2 is setto −10 mV, the current I_(out) corresponding to quantized conductance,which corresponds to (N₁−N₂ 0), flows from the first electrode to theground potential. At that time, when the current flows in the directionfrom the first electrode to the ground potential, the result of thearithmetic operation indicates a positive value. When the current flowsin the direction from the ground potential to the first electrode, theresult of the arithmetic operation indicates a negative value.

FIG. 5 shows the result of the arithmetic operation according to thethird embodiment.

The arithmetic operation of (N₁−N₂) is correctly performed. Further, ifthree or more point contacts are used, an arithmetic operation of(N₁+N₂−N₃) can be performed at a time. In this case, for example, oncondition that V1 and V2 are set to 10 mV and V3 is set to −10 mV, thearithmetic operation can be performed.

A fourth embodiment of the present invention will now be described.

According to the present embodiment, a logic circuit is constructedusing the point contacts according to the present invention. For theconfiguration of the logic circuit, in contrast to the first to thirdembodiments, the transition in the quantized conductance of each pointcontact is not used. In other words, the point contact is used as anon-off switching device. Typically, a resistance in the ON state isequal to or less than 1 kΩ and a resistance in the OFF state is equal toor more than 100 kΩ.

FIG. 6 is a schematic diagram of an OR gate formed using the pointcontacts according to the present invention.

Ag wires 21 and 22 are covered with Ag₂S 23 and 24, respectively, thusforming first electrodes. Ag bridges 25 and 26, formed on the Ag₂S 23and 24, face a Pt electrode 20 serving as a second electrode, thusforming point contacts. One end of the Pt electrode 20 is connected to areference voltage V_(S) through a resistance 27 (10 kΩ in the presentembodiment) and the other end functions as an output terminal togenerate an output voltage V_(out). Input voltage V1 and V2 are appliedto the Ag wires 21 and 22, resulting in the formation or disappearanceof the bridges 25 and 26. Thus, each point contact functions as anon-off switching device.

FIG. 7 shows the results of the operation. According to the presentembodiment, the inputs, namely, V1 and V2 are changed every second tomeasure the output V_(out).

In a two-input OR gate, for binary low-level and high-level inputs, ifeither input indicates a high level, an output must go to a high level.

The OR gate is operated using 0 V (the reference potential Vs also hasthe same value) as a low-level input and 200 mV as a high-level input.FIG. 7( a) shows the result of this case.

When either one of the two inputs V1 and V2 is 200 mV, the outputV_(out) substantially indicates 200 mV. The normal operation is foundfrom the graph. When a high-level voltage is increased to 500 mV, thesimilar result (FIG. 7( b)) is obtained.

FIG. 8 is an equivalent circuit diagram of the present logic circuit.

The reference voltage Vs and the input voltages V1 and V2 cause theformation or disappearance of the bridges 25 and 26 (FIG. 6), resultingin a change in the resistance of each of resistors R1 and R2(resistances of the point contacts formed by the bridges). Althoughthere is a small resistance R12 (about several ohms to tens of ohms)between two point contacts on the electrode 20 (FIG. 6), the resistanceis negligible as compared to R0 (10 kΩ), and R1 and R2 (1 kΩ to 1 MΩ).

First, when both of V1 and V2 are 0 V, all of the three voltagesconnected to the system indicate 0 V. Therefore, the output V_(out)necessarily indicates 0 V. Subsequently, when V1 is 0 V and V2 is 200 mV(500 mV), the bridge 25 (FIG. 6) grows and the resistance of theresistor R2 decreases. Typically, the resistance is equal to or lessthan 1 kΩ.

Consequently, since the resistance of R2 is an order or more ofmagnitude smaller than that of R0, V2′ indicates about 200 mV (500 mV).At this time, since V1′ also indicates about 200 mV (500 mV), a voltagewhereby a bridge disappears is applied to the bridge 26 (FIG. 6), sothat R1 indicates a large value of 1 MΩ or higher. Consequently, when V1is 0 V, R0, R1>>R2. Accordingly, V1′ indicates about 200 mV (500 mV)that is equivalent to V2′. Thus, the output indicates 200 mV (500 mV).To be precise, the growth of the bridge 25 and the disconnection of thebridge 26 simultaneously occur, thus causing the above-described result.

In a case where V1 is 200 mV (500 mV) and V2 is 0 V, the similarexplanation can be applied to the case. When both of V1 and V2 are 200mV (500 mV), both of the bridges 25 and 26 grow. Consequently, thevoltage of V1 and V2, namely, 200 mV (500 mV) is generated.

A fifth embodiment of the present invention will now be described.

According to the present embodiment, the configuration of an AND gatewill be described with reference to FIG. 9.

According to the present embodiment, one end of an Ag wire 30, coveredwith an Ag₂S thin film 31, is connected to a reference voltage Vsthrough a resistor 37. The other end is an output terminal. Bridges 33and 34, formed by precipitation of Ag atoms serving as mobile ions, areformed so as to face two Pt electrodes 35 and 36, respectively. Inputvoltages V1 and V2 are applied to the two Pt electrodes 35 and 36. InFIG. 9, reference numeral 32 denotes an Ag ion in the Ag₂S thin film 31.

FIG. 10 shows the results of the arithmetic operation of the AND gate.In the two-input AND gate, when both of the two inputs are at a highlevel, an output V_(out) goes to a high level.

FIG. 10( a) shows the result of the operation on condition that the highlevel is set to 200 mV. In this instance, a reference voltage is alsoset to 200 mV.

FIG. 10( b) shows the result of the operation on condition that the highlevel is set to 500 mV. In this instance, the reference voltage is 500mV.

Referring to FIG. 10, when the high level is set to 200 mV, V1 is 0 V,and V2 is 200 mV, the output V_(out) indicates a partial value (about 50mV). However, in the other cases, the output indicates 0 V as the lowlevel or 200 mV as the high level. When the high level is set to 500 mV,the normal operation is performed in all of input patterns. In the caseof the operation using 200 mV, when a critical voltage to determinelow-high levels is set to 100 mV, no problem occurs. The cause will bedescribed below.

The principle of the operation of the AND gate will be described againwith reference to FIG. 8. According to the present embodiment, thereference voltage Vs is at the high level (200 or 500 mV). First, whenboth of V1 and V2 are 0 V, both of the bridges 33 and 34 (FIG. 9) grow.Thus, the resistance of each of the resistors R1 and R2 is typicallyequal to or less than 1 kΩ. In other words, the input voltages at thelow level are connected to the output terminal through resistances whichare one order or more of magnitude smaller than the resistance R0 (10kΩ). Accordingly, the output V_(out) indicates 0 V. Subsequently, whenV1 is 0 V and V2 is 200 mV (500 mV), the bridge 33 (FIG. 9) alone grows.

On the other hand, in the bridge 34, the voltage V2′ is smaller than 200mV (500 mV) due to the voltage V1. In other words, the voltage of apolarity, which allows the bridge to disappear, is applied to the bridge34, resulting in the disappearance of the bridge 34. The resistance ofR2 is increased to about 1 MΩ. In this instance, when a potentialdifference between V2′ and V2 is small, the bridge disappearsinsufficiently. Therefore, the resistance of R2 is not increased enough.Accordingly, the above-mentioned partial output may be generated.However, when a high-level voltage is set to 500 mV, the potentialdifference between V2′ and V2 is increased enough. Thus, the completelynormal operation is realized.

The same description applies in the case where V1 is 200 mV (500 mV) andV2 is 0 V. Since the characteristics of the bridges 33 and 34 eachconstituting the point contact are slightly different from each other, anormal output is obtained in the case where an operating voltage is 200mV. Finally, when both of V1 and V2 are 200 mV (500 mV), the formationor disappearance of the bridges 33 and 34 does not occur. Since all ofvoltages are 200 mV (500 mV), an output voltage also indicates 200 mV(500 mV).

The logic circuits using the point contacts have been described.According to the foregoing embodiments, the two-input logic circuitshave been explained. When three or more point contacts according to thepresent invention are used, a logic circuit having three or more inputscan be formed on the basis of the above-mentioned principle ofoperation.

A sixth embodiment according to the present invention will now bedescribed.

A method for forming a point contact array will be described.

FIG. 11 is a diagram showing the method for forming a point contactarray according to the sixth embodiment of the present invention.

As shown in FIG. 11, Ag wires 41 and 42 are formed on an insulatingsubstrate 40. The surfaces of the Ag wires are sulfurized to form Ag₂Sfilms 43 and 44. Pt wires 45 and 46 are disposed thereon. Thus, anessential part of the point contact array is completed. It is importantthat bridges 47 and 48 comprising Ag atoms are formed at theintersections of the Ag wires 41 and 42 and the Pt wires 45 and 46, theAg wires 41 and 42 being covered with the Ag₂S films 43 and 44,respectively.

According to the present invention, therefore, when the Pt wires 45 and46 are arranged, a voltage is applied between the Pt wires 45 and 46 andthe Ag wires 41 and 42 to precipitate Ag on the Ag₂S film 43 and 44,resulting in the formation of the bridges 47 and 48. Consequently, whenthe Pt wires 45 and 46 are arranged using, for example, a wiring systemor the like, the present invention can be realized.

The bridge can be previously formed at each intersection by evaporationof Ag through a mask. Alternatively, electron beams can be irradiated oneach Ag wire covered with the Ag₂S film to precipitate Ag atoms. It isimportant that Ag exists between Ag₂S functioning as a first electrodeand Pt functioning as a second electrode.

Furthermore, Pt wires can be previously formed on another substrate andbe then adhered to the substrate having the Ag wires covered with theAg₂S films.

A seventh embodiment of the present invention will now be described.

A method for forming another point contact array and the structurethereof will be described.

FIG. 12 is a schematic view of a point contact array according to theseventh embodiment of the present invention, the point contact arraycontrolling the conductivity of each semiconductor.

Referring to FIG. 12, Ag wires 51 and 52, respectively covered with Ag₂Sfilms 53 and 54, are formed on an insulating substrate 50. Further,semiconductors or insulators 57, 58, 59, and 60, which can dissolve Agatoms, are formed only at the intersections of the Ag wires 51 and 52and the Pt wires 55 and 56. In FIG. 12, an insulating material coveringthese components are not shown. All of the components shown in thediagram are embedded in a device.

In this case, according to the same principle as that described above,Ag ions move from the Ag₂S films 53 and 54. The moving Ag ions aredissolved into the semiconductors or insulators 57, 58, 59, and 60 tochange the conductivity of each semiconductor or insulator. Thus, thesimilar effects as those in the above-mentioned embodiments can berealized. In this case, since a space where the formation ordisappearance of the bridges is not needed in the device, thesecomponents can be easily embedded in an insulating member.

When Ag thin films are previously formed in place of the semiconductorsor insulators, the same structure as that described in the sixthembodiment is obtained. In this case, Ag atoms contained in the Ag thinfilms enter the Ag₂S films, resulting in the disappearance of the thinfilm.

According to the present invention, crystals or amorphous materials ofGeS_(x), GeSe_(x), GeTe_(x), or WO_(x) (0<x<100) are used as thesemiconductors or insulators which can dissolve the Ag ions.

An eighth embodiment of the present invention will now be described.

FIG. 13 shows an embodiment in which a part of each metallic wireserving as a first electrode is covered with an electronic/ionic mixedconductor. According to the present embodiment, it is enough to formpoint contacts, each comprising “a metal serving as a first electrode,an electronic/ionic mixed conductor, a bridge or a semiconductor, and ametal serving as a second electrode”, at the intersections of themetallic wire functioning as the first electrode and metallic wires eachfunctioning as the second electrode.

Therefore, as shown in FIG. 13, when electronic/ionic mixed conductors73 and 74 are formed only in the vicinity of the intersections of ametallic wire 70 functioning as a first electrode and metallic wires 71and 72 each functioning as a second electrode, a point contact (bridge)75 can be formed between the electronic/ionic mixed conductor 73 and themetallic wire 71 and a point contact (bridge) 76 can be formed betweenthe electronic/ionic mixed conductor 74 and the metallic wire 72.

Furthermore, for the metal serving as the first electrode, each partwhich is in contact with the electronic/ionic mixed conductor can bedifferent from a material of the wire between the point contacts.According to the present embodiment, for example, Ag wires 79 and 80 areused as parts which are in contact with electronic/ionic mixedconductors (Ag₂S) 77 and 78, respectively. Tungsten wires are used asother parts 81 to 83. For the material of each part to be in contactwith the electronic/ionic mixed conductor, it is necessary that eachpart comprise the same element as the mobile ions in theelectronic/ionic mixed conductor. According to the present embodiment,therefore, since Ag₂S is used as the electronic/ionic mixed conductor,Ag is used as a material for the part which is in contact therewith.

A NOT circuit according to another embodiment of the present inventionand an electronic circuit using the same will now be described in detailhereinbelow.

FIG. 14 is a schematic diagram of a NOT circuit according to a ninthembodiment of the present invention.

As shown in the diagram, a first electrode 102 serving as anelectronic/ionic mixed conductor is formed on a conductive substance101. A potential difference between the first electrode 102 and a secondelectrode 103 is controlled, thus controlling so that mobile ions(atoms) 104 in the electronic/ionic mixed conductor are precipitated asmetallic atoms on the surface of the first electrode 102, alternatively,the precipitated metallic atoms are dissolved as mobile ions (atoms)into the first electrode 102. In other words, when a proper negativevoltage is applied to the second electrode 103 with respect to the firstelectrode 102, the mobile ions (atoms) 104 in the electronic/ionic mixedconductive material is precipitated due to the effect of voltage andcurrent, thus forming a bridge 105 between the electrodes 102 and 103.Consequently, resistance between the electrodes 102 and 103 decreases.

On the contrary, when a proper positive voltage is applied to the secondelectrode 103, the mobile ions (atoms) 104 are dissolved into theelectronic/ionic mixed conductive material, resulting in thedisappearance of the bridge 105. In other words, the resistanceincreases. Hereinbelow, such a two-terminal device will be called an“atomic switch”. Japanese Patent Application No. 2000-265344, by theinventors of the present application, proposes the detailed principle ofoperation thereof.

A voltage VH/2 corresponding to a high-level output is applied to thesecond electrode 103 of the atomic switch through a resistor 106(resistance R1). An input terminal V_(in) is connected to the secondelectrode 103 through a capacitor 108 (capacitance C1). On the otherhand, a voltage VL corresponding to a low-level output is applied to theconductive substance 101 functioning as the first electrode 102 of theatomic switch through a resistor 107 (resistance R2). An output terminalV_(out) is connected to the conductive substance 101.

It is assumed that R(ON) denotes a resistance of the atomic switch inthe ON state and R(OFF) denotes a resistance thereof in the OFF state.According to the present invention, the resistors and the atomic switchwhich satisfy the following relation are used.R(OFF)>>R 2>>R(ON)˜R 1

For the input V_(in), VH is used as a high-level input and VL is used asa low-level input. When the input V_(in) is VL, the output V_(out)indicates VH/2. When the input V_(in) is VH, the output V_(out)indicates VL. In other words, when the input is at a high level, theoutput goes to a low level. When the input is at a low level, the outputgoes to a high level. Thus, the atomic switch functions as a NOTcircuit.

Hereinbelow, an embodiment using an atomic switch, in which Ag₂S formedon Ag is used as the first electrode 102 and Pt is used as the secondelectrode 103, will now be described. It is needless to say that a NOTcircuit can be formed using an atomic switch having anotherelectronic/ionic mixed conductor such as Ag₂Se, Cu₂S, or Cu₂Se and ametal other than Pt.

As mentioned above, according to the present invention, the use of theatomic switch, serving as a two-terminal device comprising the firstelectrode 102 made of an electronic/ionic mixed conductive material andthe second electrode 103 made of a conductive substance, realizes a NOTcircuit comprising only the two-terminal devices.

In this instance, the case where VH is used as the high-level inputV_(in) and VL (0 V) is used as the low-level input will be used as anexample and the principle of operation of the NOT circuit shown in FIG.14 will now be described in detail with reference to FIG. 15.

When the input V_(in) changes from a low level (VL) to a high level (VH)at time t1 [refer to FIG. 15( a)], charges Q=C1×VH (C1 denotes thecapacitance of the capacitor) are accumulated in the capacitor 108. Atthis time, a potential V_(in)′ of the second electrode 103 of the atomicswitch changes due to a current, which temporarily flows, as shown inFIG. 15( b). In other words, the potential of the second electrode 103of the atomic switch is temporarily higher than that of the firstelectrode 102, so that the atomic switch changes to the OFF state (highresistance) [refer to FIG. 15( c)]. Thus, R(OFF)>>R2. The output V_(out)indicates VL [refer to FIG. 15( d)].

Since the resistance of the atomic switch is increased, the potentialbetween the electrodes 102 and 103 of the atomic switch is increased asshown in FIG. 15( e). Switching time ts is almost determined by thecapacitance C1 of the capacitor 108 and the resistance R1 of theresistor 106. For instance, when it is assumed that the capacitance C1of the capacitor is 1 pF and the resistance R1 is 10Ω, switching can beperformed on the order of gigahertzs.

On the other hand, when the input V_(in) changes from the high level(VH) to the low level (VL) at time t2 [refer to FIG. 15( a)], thecharges accumulated in the capacitor 108 are discharged. Due to acurrent which temporarily flows, the potential V_(in)′ of the secondelectrode 103 of the atomic switch changes as shown in FIG. 15( b). Inother words, the potential of the second electrode 103 in the atomicswitch is temporarily remarkably lower than that of the first electrode102, so that the atomic switch changes to the ON state (low resistance)[refer to FIG. 15( c)]. Consequently, R2>>R(ON). The output V_(out)indicates VH/2 [refer to FIG. 15( d)].

FIG. 15( e) shows the potential difference between the electrodes 102and 103 of the atomic switch. When the input V_(in) is at the low level(VL), the potential difference between the electrodes 102 and 103 of theatomic switch indicates about zero. Thus, the ON state of the atomicswitch is held stably. On the other hand, when the input V_(in) is atthe high level (VH), the potential difference between the electrodes 102and 103 of the atomic switch indicates VH/2. This value indicates thepotential difference at which the atomic switch should be in the OFFstate. Therefore, the OFF state is held stably. In other words, the NOTcircuit according to the present embodiment operates with reliabilityand stability.

According to the present embodiment, the case where VH or VL is used asan input and VH/2 or VL is used as an output is described. In the NOTcircuit shown in FIG. 14, according to the principle of operation of theatomic switch, under limitations that a potential difference betweeninputs (in the present embodiment, VH−VL) has to always be larger than apotential difference between outputs (in the present embodiment,VH/2−VL), the potential difference between inputs and that betweenoutputs can be freely set within the limitations.

In the eleventh and twelfth embodiments, a case where the potentialdifference between inputs is equivalent to that between outputs will bedescribed in detail. In other words, according to the present invention,a NOT circuit in which the level of an input is equivalent to the levelof an output can be formed.

FIG. 16 is a schematic diagram of a NOT circuit according to a tenthembodiment of the present invention.

A NOT circuit comprising two-terminal devices with arrangement differentfrom that shown in FIG. 14 will now be described as another embodiment.

The used components are exactly the same as those shown in FIG. 14according to the ninth embodiment. In other words, a first electrode 112serving as an electronic/ionic mixed conductor (Ag₂S) is formed on Ag111 serving as a conductive substance. Mobile ions (Ag ions) 114 in theelectronic/ionic mixed conductor are precipitated to form a bridge 115comprising Ag atoms between the first electrode 112 and a secondelectrode (Pt) 113. An atomic switch with the above structure is used.

A voltage VH/2 corresponding to a high-level output is applied to thesecond electrode (Pt) 113 of the atomic switch through a resistor 116(resistance R3). An output terminal V_(out) is connected to the secondelectrode 113.

On the other hand, a voltage VL corresponding to a low-level output isapplied to the conductive substance (Ag) 111 constituting the firstelectrode 112 of the atomic switch through a resistor 117 (resistanceR4). An input terminal V_(in) is connected to the first electrode 112through a capacitor 118 (capacitance C2).

It is assumed that R(ON) denotes a resistance of the atomic switch inthe ON state and R(OFF) denotes a resistance of the atomic switch in theOFF state. According to the present embodiment, the resistors and theatomic switch, which satisfy the following relation, are used.R(OFF)>>R 3>>R(ON)˜R 4

The principle of operation of the NOT circuit shown in FIG. 16 will nowbe described in detail with reference to FIG. 17.

When the input V_(in) changes from a low level (VL) to a high level (VH)at time t1 [refer to FIG. 17( a)], charges Q=C2×VH (C2 denotes acapacitance of the capacitor) are accumulated in the capacitor 118. Atthis time, a potential V_(in)′ of the first electrode 112 in the atomicswitch changes due to a current, which temporarily flows, as shown inFIG. 17( b). In other words, the potential of the first electrode 112 inthe atomic switch is temporarily remarkably higher than that of thesecond electrode 113, so that the atomic switch changes to the ON state(low resistance) [refer to FIG. 17( c)].

Thus, R3>>R(ON). The output V_(out) indicates VL [refer to FIG. 17( d)].Switching time ts is almost determined by the capacitance C2 of thecapacitor 118 and the resistance R4 of the resistor 117. For instance,when it is assumed that the capacitance C2 of the capacitor is 1 pF andthe resistance R4 is 10Ω, switching can be performed on the order ofgigahertzs.

On the other hand, when the input V_(in) changes from the high level(VH) to the low level (VL) at time t2 [refer to FIG. 17( a)], thecharges accumulated in the capacitor 118 are discharged. Due to acurrent which temporarily flows, the potential V_(in)′ of the firstelectrode 112 in the atomic switch changes as shown in FIG. 17( b). Inother words, the potential of the first electrode 112 in the atomicswitch is temporarily remarkably lower than that of the second electrode113, so that the atomic switch changes to the OFF state (highresistance) [refer to FIG. 17( c)]. Consequently, R(OFF)>>R3. The outputV_(out) indicates VH/2 [refer to FIG. 17( d)].

FIG. 17( e) shows the potential difference between the electrodes 112and 113 of the atomic switch. When the input V_(in) is at the low level(VL), the potential difference between the electrodes 112 and 113 of theatomic switch indicates VH/2. This value indicates a potentialdifference at which the atomic switch should be in the OFF state.Therefore, the OFF state is held stably.

On the other hand, when the input V_(in) is at the high level (VH), thepotential difference between the two electrodes 112 and 113 of theatomic switch indicates substantially zero. Thus, the ON state of theatomic switch is held stably. In other words, the NOT circuit accordingto the present embodiment operates with reliability and stability.

According to the embodiment, the case where VH and VL are used as inputsand VH/2 and VL are used as outputs is described. In the same case asthe NOT circuit according to the ninth embodiment (FIG. 14), underlimitations that a potential difference between inputs has to always belarger than a potential difference between outputs, the potentialdifference between inputs and that between outputs can be freely setwithin the limitations.

For the arrangement of the atomic switch, the resistors, and thecapacitor, and the number of each device, the pattern other than that ofthe above-mentioned embodiment can be made. The principalcharacteristics of the present invention are to use the above devices ascomponents.

FIG. 18 is a schematic diagram of a NOT circuit according to theeleventh embodiment of the present invention. FIG. 19 includes graphsshowing the principle of operation of the NOT circuit shown in FIG. 18.

The NOT circuit in which a potential difference between inputs isequivalent to that between outputs will now be described. A diode 109 isconnected to a portion (V_(out)′ in FIG. 18) corresponding to the outputof the NOT circuit according to the ninth embodiment (FIG. 14). VH isapplied to the other end of the diode 109 through a resistor 110(resistance R5). An output terminal V_(out) is connected to the otherend thereof. Further, the present NOT circuit differs from the NOTcircuit according to the ninth embodiment (FIG. 14) with respect to apoint that a voltage to be applied through the resistor 107 (resistanceR2) is not VL, but VS.

The potential of V_(out)′ is changed in the same way as the ninthembodiment except that the low level is not VL, but VS [refer to FIG.19( b)]. According to the present embodiment, by satisfying the relationof VH/2<VF(VH−VS) (VF denotes a threshold voltage of the diode 109), thepotential difference between inputs is equalized to that between outputsin the NOT circuit. In other words, when V_(out)′ indicates VH/2, avoltage that is equal to or lower than the threshold voltage is appliedto the diode 109. It is assumed that RB denotes a resistance of thediode 109 at this time and RF denotes a resistance thereof when avoltage that is equal to or higher than the threshold. The resistor 110which satisfies the relation of RB>>R5>>RF is used. FIG. 19( c) shows avoltage to be applied to the diode. The resistances and a voltage to beapplied are set so as to satisfy the following expressions.R 5/R 2=(VH−VL)/(VL−VF−VS)VL>VF+VSThus, the output V_(out) is changed as shown in FIG. 19( d). In otherwords, the NOT circuit in which the potential difference between inputsis equivalent to that between outputs can be realized.

FIG. 20 is a schematic diagram of a NOT circuit according to a twelfthembodiment of the present invention.

A NOT circuit in which a potential difference between inputs isequivalent to that between outputs can be formed on the basis of the NOTcircuit according to the tenth embodiment shown in FIG. 16. A diode 119is connected to a portion (V_(out)′) corresponding to the output of theNOT circuit according to the tenth embodiment (FIG. 16). VH is appliedto the other end of the diode 119 through a resistor 120 (resistanceR6). An output terminal V_(out) is connected to the other end thereof.Further, the present NOT circuit differs from the NOT circuit accordingto the tenth embodiment with respect to a point that the voltage appliedthrough the resistor 117 (resistance R4) is not VL, but VS.

The principle of operation is substantially the same as that of the NOTcircuit described in the eleventh embodiment. The resistor 120 whichsatisfies the relation of RB>>R6>>RF is used and the resistances and avoltage to be applied are set so as to satisfy the followingexpressions.R 6/2R 4=(VH−VL)/(VL−VF−VS)VL>VF+VSOn this condition, the NOT circuit in which the potential differencebetween inputs is equivalent to that between outputs can be realized. Inthe above case, the resistance of the atomic switch is substantiallyequivalent to R4. When the condition does not apply, it is necessary tocontrol VS to some extent.

When the diode and the resistor are added to the NOT circuit in whichthe atomic switch, the resistors, and the capacitor are arrangedaccording to various patterns, the above-mentioned NOT circuit in whichthe potential difference between inputs is equivalent to that betweenoutputs can be constructed. In other words, the arrangement of theatomic switch, the resistors, the capacitor, and the diode is notlimited to that described in the present embodiment. The presentinvention is characterized in that these devices are used as components.

FIG. 21 is a schematic diagram of a one-digit binary adder according toa thirteenth embodiment of the present invention.

According to the present embodiment, a case where the one-digit binaryadder comprises a NOT circuit according to the present invention, an ANDcircuit, and an OR circuit, the AND circuit and the OR circuit eachhaving an atomic switch, will be described.

The NOT circuit according to the eleventh embodiment shown in FIG. 18 isused. The AND circuit and the OR circuit, proposed by the inventors ofthe present application in Japanese Patent Application No. 2000-334686,are used. In the diagram, respective parts corresponding to the NOTcircuit, the AND circuit, and the OR circuit are surrounded by dottedlines. In other words, the present one-digit binary adder comprises twoNOT circuits 121 and 122, three AND circuits 123, 124, and 125, and oneOR circuit 126.

FIG. 22 shows the circuits using logical symbols. In FIG. 22, referencenumerals 121′ and 122′ denote the NOT circuits, 123′, 124′, and 125′denote the AND circuits, and 126′ denotes the OR circuit.

For inputs X and Y, it is assumed that a high-level input indicates 1and a low-level input indicates 0. Outputs S and C are as shown in FIG.23. According to the present invention, the one-digit binary adder,which is applied to a computer, can be constructed. This case is oneexample. According to the present invention, a NOT circuit, an ANDcircuit, and an OR circuit can be constructed using two-terminaldevices. Accordingly, all of logic circuits can be constructed usingonly the two-terminal devices.

The present invention is not limited to the above embodiments. Variousmodifications are possible on the basis of the spirit of the presentinvention and are not excluded from the scope of the present invention.

As mentioned above, according to the present invention, the followingadvantages can be obtained.

(A) A high-speed point contact array with low power consumption can beconstructed, resulting in the realization of a multiple recording memorydevice, a logic circuit, and an arithmetic circuit.

(B) Since a NOT circuit can be constructed using two-terminal devices,all of logic circuits can be realized using only the two-terminaldevices. A nanometer-sized atomic switch can be easily formed. Accordingto the present invention, therefore, a nanometer-scale device can berealized.

INDUSTRIAL APPLICABILITY

A point contact array, a NOT circuit, and an electronic circuit usingthe same according to the present invention are applicable to a logiccircuit, an arithmetic circuit, and a memory device which arenano-scale.

1. A point contact array comprising a plurality of electronic devices,each of which comprises a first electrode made of a compound conductivematerial having ionic conductivity and electronic conductivity and asecond electrode made of a conductive substance, wherein the first andsecond electrodes are arranged so as not to be in direct contact witheach other and form a space therebetween, and each of the electronicdevices can control conductance between the electrodes by means ofcontrolling formation and deformation of a bridge of metal atoms withinthe space.
 2. The point contact array according to claim 1, wherein thecompound conductive material having mobile ions (M ion: M denotes ametallic atom) is formed on a source of the mobile ions (M).
 3. Thepoint contact array according to claim 1, wherein the compoundconductive material is Ag₂S, Ag₂Se, Cu₂S, or Cu₂Se.
 4. The point contactarray according to claim 1, wherein a semiconductor or insulatormaterial, which can dissolve ions and which exhibits electronicconductivity and ionic conductivity due to the dissolution of ions, isarranged between the first and second electrodes, and mobile ionscontained in the compound conductive material enter the semiconductor orinsulator material to change the conductance of the semiconductor orinsulator.
 5. The point contact array according to claim 4, wherein thesemiconductor or insulator material is a crystal or an amorphousmaterial of GeS_(x), GeSe_(x), GeTe_(x), or WO_(x) (0<x<100).
 6. Thepoint contact array according to claim 1, wherein a metallic wire, ofwhich at least one part is covered with the compound conductivematerial, functions as the first electrode, a metallic wire functions asthe second electrode, a plurality of metallic wires functioning as atleast one of the electrodes exist, and a point contact is arranged ateach intersection of the metallic wires.
 7. The point contact arrayaccording to claim 1, wherein the conductance of each point contact isquantized.
 8. The point contact array according to claim 7, functioningas a multiple recording memory device in which the quantized conductanceof each point contact is used as a recording state.
 9. The point contactarray according to claim 7, wherein the quantized conductance of eachpoint contact is used as an input signal, and the potentials of therespective electrodes are controlled to perform addition or subtractionof the input signals.
 10. The point contact array according to claim 1,functioning as a logic circuit in which a potential at one end of eachpoint contact is used as an input signal.